Subject: Re: Re: [TI994A] Back to some hardware related questions.....

From: [email-masked]
Date: Mon, 02 Nov 2009 13:29:07 -0600 (CST)

Tursi is correct here. There are just a couple of points I would add that I learned from the SCSI upgrade project and SNUG (Michael Becker). Design of the circuits can play a role in logic timing. For instance, ground busses that are narrow (Especially those that surround the board and are the trunk path for all the logic.) may impede current as we push the logic to pulse faster and faster. Design wide ground busses. Narrow RAM chips can be to fast for certain circuits. This was a problem with the SCSI version "G" card and Michael had little boards made so we could use the standard wide chip static RAM in place of the narrow chip in the 1.6 upgrades. For circuits that really get pulsing you may want to use tantalums in place of electrolytics so you don't run out of capacitance. A good rule is to use electrolytics close to the power suppy and tantalums out on the board. The more I play with TI hardware the more I realize what an art good design is. ;)

Nov 2, 2009 12:26:34 PM, [email-masked] wrote:

> When using IC's such as SRAMS and the like that have a chip enable pin, 
> are there any special considerations timing wise as to when that pin has 
> to go low versus when the address and data lines are presented or can 
> all the logic that controls them be toggled at once ? (I'll clarify if 
> needed.)

Generally you are fine to toggle them all at once. The low speeds on the 
TI bus mean you'll be fine pretty much every time, no matter what you do.

For the nitty gritty answers, that's when you start looking at the timing 
diagrams in the datasheets. They will show you the exact relationship 
between the state changing and the data being (or needing to be valid), 
and so forth. You would then compare those against the timing charts for 
the processor/system you are connecting to.

But with a modern memory chip on the TI bus, you're fine.

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From: "Tursi" <[email-masked]>
Date: Mon, 2 Nov 2009 15:00:41 -0500

> Tursi is correct here. There are just a couple of points I would add 
> that I learned from the SCSI upgrade project and SNUG (Michael 
> Becker). Design of the circuits can play a role in logic timing. For 
> instance, ground busses that are narrow (Especially those that 
> surround the board and are the trunk path for all the logic.) may 
> impede current as we push the logic to pulse faster and faster. Design 
> wide ground busses. Narrow RAM chips can be to fast for certain 
> circuits. This was a problem with the SCSI version "G" card and 
> Michael had little boards made so we could use the standard wide chip 
> static RAM in place of the narrow chip in the 1.6 upgrades. For 
> circuits that really get pulsing you may want to use tantalums in 
> place of electrolytics so you don't run out of capacitance. A good 
> rule is to use electrolytics close to the power suppy and tantalums 
> out on the board. The more I play with TI hardware the more I realize 
> what an art good design is. ;)
>

Great tips.. saving that! :)