Subject: Back to some hardware related questions.....

From: "Marc H" <[email-masked]>
Date: Mon, 02 Nov 2009 16:39:51 -0000

When using IC's such as SRAMS and the like that have a chip enable pin, are there any special considerations timing wise as to when that pin has to go low versus when the address and data lines are presented or can all the logic that controls them be toggled at once ? (I'll clarify if needed.)

Additionally it appears that my little CRU circuit board is functioning as it should but that doesn't mean it is (especially since it is not connected to anything.)  If someone out there would be so kind as to look at my schematic and advise me as to whether this should work when connected to a TI (address lines, data lines correct etc.) I'd appreciate it.  I'd have to EM it later this afternoon.

Thanks, Marc

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From: tursi <[email-masked]>
Date: Mon, 2 Nov 2009 09:26:32 -0800 (PST)

> When using IC's such as SRAMS and the like that have a chip enable pin, 
> are there any special considerations timing wise as to when that pin has 
> to go low versus when the address and data lines are presented or can 
> all the logic that controls them be toggled at once ? (I'll clarify if 
> needed.)

Generally you are fine to toggle them all at once. The low speeds on the 
TI bus mean you'll be fine pretty much every time, no matter what you do.

For the nitty gritty answers, that's when you start looking at the timing 
diagrams in the datasheets. They will show you the exact relationship 
between the state changing and the data being (or needing to be valid), 
and so forth. You would then compare those against the timing charts for 
the processor/system you are connecting to.

But with a modern memory chip on the TI bus, you're fine.