Subject: logic questions

From: "Marc H" <[email-masked]>
Date: Sun, 06 Dec 2009 01:41:01 -0000

1)  When building with logic chips does it make any real difference whether you build in linear chains or you create a tree structure (I'll elaborate if needed.)

2)  Do elements that need extra massaging (such as inversion) need to be placed after elements that go straight from the buss to the IC.

3)  How critical is timing (like the above) to your average 73LS series chips.

Thanks...

Frustrated Marc

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From: "Tursi" <[email-masked]>
Date: Sat, 5 Dec 2009 22:15:12 -0500

> 1)  When building with logic chips does it make any real difference 
> whether you build in linear chains or you create a tree structure (I'll 
> elaborate if needed.)
>

You just need to keep load in mind, really. Remember that circuitry is not 
sequential like software, every path is taken at the same time.

> 2)  Do elements that need extra massaging (such as inversion) need to be 
> placed after elements that go straight from the buss to the IC.
>

I don't quite follow this question... but remember that "the bus" is just a 
set of lines coming from another IC.

> 3)  How critical is timing (like the above) to your average 73LS series 

The datasheet will tell you exactly how critical timing is to each chip in 
question. Generally you'll be looking at switching times in the nanoseconds.

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From: "sconner3uk" <[email-masked]>
Date: Sun, 06 Dec 2009 10:19:51 -0000

It depends what you're doing. If you're doing things like memory address decoding, then a logic chip's 'propogation delay' is very short compared with the TI's memory access time - all the address decoding chips will have sorted themselves out by the time the TI comes to read or write to memory. If you're doing things like using clocks to latch data then you need a bit of care: consider the following - you're using a string of gates to derive a signal you want to latch, but the clock signal only goes through one gate. It is possible for the gates to delay the signal you want to latch until *after* the clock pulse - so you'll latch the wrong data. It all depends on the relative timing of the source signals of course ...

Stuart.