Subject: HDC9234: Need expert help.

From: "Michael Zapf" <[email-masked]>
Date: Tue, 27 Apr 2010 20:27:57 -0000

I guess the following problem can only be cleared up by someone who has studied the functionality of the HDC9234 used on the HFDC, has written a driver or the DSR. So I apologize if the following sounds to you like a random arrangements of words. :-)

My problem relates to the STB*/S0/S1 handling.

While testing my HFDC implementation in MESS I sometimes had problems with stepping. The verify phase failed as the head was not on the expected cylinder. This was caused by changing the selected drive; I failed to copy the drive status of the newly selected drive from the latch into the drive status register in time, so the track00 line state was outdated. I added more synchronization points in the code, making that work reliably. And now formatting was broken.

This brought me to a question which I cannot fully solve with the specification. Either I just have not found it, misunderstood it, or it is really missing. How do STB*/S0/S1 work?

From the description I assumed that the contents of the registers output1 and output2 are asynchronously synched with the external latches (and drive status in the opposite direction), since there is no proper command for that. I assumed that the STB* signal goes low regularly, and that S0/S1 go through a 00/01/10/11 sequence. So when I call the "drive select" command I just set the bits in the internal register, and some short time later, the contents are propagated to the external latch. Likewise, when the drive status changes, the latch is copied to the internal register at some unknown but close time.

In the HFDC, the floppy selection is not done via "drive select" but by setting the "user output" bits in the "retry count" register. Again, these bits of this register are part of the output1 register and somehow/sometime get propagated to the latch.

So far so good.

Now when I want to format the disk I have to call the "format track" command, but before (as usual) I need to set up the registers of the controller appropriately. For this command the registers change their meaning, including the "retry count" which now contains >FD (one's complement for 2, which is 2*128=256 byte sector size). 

And now my problem is here: After setting the "retry count" to >FD, my implementation synched that to the external latch. This instantly deselected the current disk drive, and the formatting failed. 

What I don't understand: How does the controller know that it will receive a "format track" command in the near future and so avoid to acccidentally propagate the value of the retry count to the external selection logic behind the latch? 

The only solution to this could be that my assumption is wrong - that STB*, S0, S1 state changes are not running in the background. So probably the "drive select" is responsible for triggering the sync, but this is not clearly stated in the specification.

Any idea? I mean I could just assume that only "drive select" can cause the sync of the latches with the internal registers, but I'd prefer to find that in the spec somewhere.

All for now,

Michael

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From: "Michael Zapf" <[email-masked]>
Date: Mon, 03 May 2010 21:53:00 -0000

In the meantime I found a way to solve that problem or at least to make it go away. I decided that the chip is intelligent enough to propagate the settings only at times when it does not spoil its own operation. 

But there is a new problem (hopefully the last one). BTW, I'm talking about MESS (parts of the description may sound like happening with the real hardware).

I have some problems with reading single density disks on the HFDC. Actually, I did not have the problems until I built in a check whether medium density and controller density settings match (so I called for problems, and I got them. :-) )

In fact, when I try to read a SSSD disk with the HFDC, it tries several times to read it as DD, but fails to fall back to SD. The interesting fact is that MDOS does it right! 

********

Tim - do you remember something like having to work around such an issue?

********

I had a look at the HFDC sources and traced the execution in MESS, and indeed there is something strange happening - it does set the density to single, but later it (falsely) concludes that it is operating the hard disk and puts the density selection to HD.

I thought I should have run into problems with the controller, since I actually used an HFDC, and I would have remembered being unable to read my first disks - but then I also recalled that before using the HFDC I had the Myarc DDCC and I got the HFDC *after* switching to the Geneve (which replaces the DSR). So maybe I never used the native DSR of the HFDC.

Michael

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From: ti99_forever <[email-masked]>
Date: Tue, 4 May 2010 13:44:45 -0700 (PDT)

Michael,

I think you've uncovered a real issue. I had a great deal of problems reading single-density disks when I got my HFDC. IIRC, I had to install my TI disk controller alongside the HFDC to convert these disks over to a drive connected to the HFDC.

Tim probably already figured this one out, though...;)

--- On Mon, 5/3/10, Michael Zapf <[email-masked]> wrote:

From: Michael Zapf <[email-masked]>
Subject: [TI994A] Problem solved, but now single density issue on HFDC
To: [email-masked]
Date: Monday, May 3, 2010, 5:53 PM

********

********

Michael

------------------------------------

Yahoo! Groups Links

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From: "Michael Zapf" <[email-masked]>
Date: Tue, 04 May 2010 21:30:01 -0000

I found it. Was just an intuition, but seemingly the right one.

Raphael Nabet (who originally wrote the HFDC emulation) emulated the dip switches on the board by one byte, covering 4*2 bits. There is one flag for choosing between 40 track drives and 80 track drives. Selecting 40 track drives yields the value >55, while 80 track drives get a >00. After inverting and reverting the sequence, we get a 01 for a 40 track drive and 11 for an 80 track.

But 11 not only means 80 tracks but also high density (36 sectors). However, he himself wrote in the comments that the DSR is buggy with respect to HD drives. And one of the bugs obviously is the recent one. The drive is unable to read a single density disk if the dip switch pair is set to 11.

So I changed the switch setting to >AA (= 10 10 10 10) ... and voila - there it is: All OK now. :-)

(Just had another look in the manual: There is only one sector count 36 for this setting. So it's possibly intended? 11 means *only* HD, no smaller sizes, probably because it also adjusts the clock divider on the board and may be unable to re-adjust the divider to accomodate to less dense formats.)

Michael

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From: Insane Multitasker <[email-masked]>
Date: Tue, 4 May 2010 20:21:00 -0500

You give me too much credit, sir  ;)   I just used my Myarc FDC since it wrote most of the  disks in my library anyway. One more more reason my Geneve case contains IDE, SCSI, HFDC, Horizon, Myarc FDC, and RS232, and the Geneve <grin>  Oh, and one slot for periodic testing with Myarc 512K and Rave memory cards.  Never really had much need 
or desire for the Speech ;)

Michael, the MDOS DSR makes *heavy* useage of the HFDC DSR up to and including
comments.  Between it and the HFDC source you're sure to find the problem.  Are you
trying to use SD with HD?  

To: [email-masked]
From: [email-masked]
Date: Tue, 4 May 2010 13:44:45 -0700
Subject: Re: [TI994A] Problem solved, but now single density issue on HFDC

Michael,

In the meantime I found a way to solve that problem or at least to make it go away. I decided that the chip is intelligent
 enough to propagate the settings only at times when it does not spoil its own operation. 

********

********

I had a look at the HFDC sources and traced the execution in MESS, and indeed there is something strange happening - it does set the density to single, but later
 it (falsely) concludes that it is operating the hard disk and puts the density selection to HD.

Michael

Yahoo! Groups Links

    

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