Subject: CRU / TMS9901 challenging question

From: "Michael Zapf" <[email-masked]>
Date: Tue, 05 Jul 2011 21:08:04 -0000

Here's another technical challenge, maybe some of you can give me a hint or convince me of another conclusion.

Question: What is the meaning of the SBO >0002 line in the TI console ROM at location 094A?

Some information on that: 

Address >0004 (bit 2) of the CRU is named /INT2 and is connected to /INT of the VDP.

I had a look at Heiner Martin's "TI Intern" book (many of you certainly know about it), and I found the comment "Clear VDP interrupt". This sounds plausible, but it can't be true.

The problem is that the TMS9901 has a dual function on its interrupt line bits. You can read their state with TB, and you can load a value into them with SBO and SBZ. However, loading a value does not change the input latch contents - it sets or resets the mask for this input. The mask is ANDed to the inverted latch value, so you can attach or detach interrupt inputs with SBO/SBZ. (Also see Figure 3 in the description TMS9901.pdf on WhTech.)

I put a printf into the MESS emulation and found that (as expected) the mask for /INT2 is never set to 0 but is always 1. In contrast, if the value had been 0 (so SBO would make sense), the /INT2 would have been masked away, which would block VDP interrupts, so this code would never be reached. 

(Blocking VDP interrupts is usually done within the CPU, using the LIMI operation.)

It may sound a bit bold, but I conclude that the line in the console ROM does not make sense. Maybe the engineers misunderstood the 9901 operation at that point.

Any other ideas?

Michael

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From: mark wills <[email-masked]>
Date: Tue, 5 Jul 2011 22:44:41 +0100 (BST)

Overwrite the instruction with a NOP and see what happens ;-)

Maybe not so silly as it sounds?

Mark

>________________________________
>From: Michael Zapf <[email-masked]>
>To: [email-masked]
>Sent: Tuesday, 5 July 2011, 22:08
>Subject: [TI994A] CRU / TMS9901 challenging question
>
>------------------------------------
>
>Yahoo! Groups Links
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From: "Jens-Eike Hartwig" <[email-masked]>
Date: Wed, 06 Jul 2011 00:44:18 +0200

If not the console code, maybe a DSR contains the SBZ instruction to
mask out the VDPINT. The RS232 (or any other card) is serviced as
interrupt level 1 (IC0-IC3 are hard-wired to level 1), the DSR can
distinguish its own interrupt from the VDPINT by blocking it with SBZ 2
(?). Or, it is a way not to have a routine interrupted, where the GROM
or VDP address is manipulated. The SBO 2 re-sets interrupt behaviour to
normal (VDPINT allowed).

Jens-Eike

-----Original Message-----
Date: Tue, 05 Jul 2011 23:08:04 +0200
Subject: [TI994A] CRU / TMS9901 challenging question
From: "Michael Zapf" <[email-masked]>
To: [email-masked]

Here's another technical challenge, maybe some of you can give me a hint
or convince me of another conclusion.

Question: What is the meaning of the SBO >0002 line in the TI console
ROM at location 094A?

Address >0004 (bit 2) of the CRU is named /INT2 and is connected to /INT
of the VDP.

I had a look at Heiner Martin's "TI Intern" book (many of you certainly
know about it), and I found the comment "Clear VDP interrupt". This
sounds plausible, but it can't be true.

The problem is that the TMS9901 has a dual function on its interrupt
line bits. You can read their state with TB, and you can load a value
into them with SBO and SBZ. However, loading a value does not change the
input latch contents - it sets or resets the mask for this input. The
mask is ANDed to the inverted latch value, so you can attach or detach
interrupt inputs with SBO/SBZ. (Also see Figure 3 in the description
TMS9901.pdf on WhTech.)

I put a printf into the MESS emulation and found that (as expected) the
mask for /INT2 is never set to 0 but is always 1. In contrast, if the
value had been 0 (so SBO would make sense), the /INT2 would have been
masked away, which would block VDP interrupts, so this code would never
be reached. 

(Blocking VDP interrupts is usually done within the CPU, using the LIMI
operation.)

It may sound a bit bold, but I conclude that the line in the console ROM
does not make sense. Maybe the engineers misunderstood the 9901
operation at that point.

Any other ideas?

Michael

Yahoo! Groups Links

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From: "Stuart" <[email-masked]>
Date: Tue, 05 Jul 2011 23:05:17 -0000

(I think I've had a message disappear into the ether, so this might appear twice ...)

When the TMS9901 is reset (which also occurs at power-up), all the interrupts are masked, so you need a SBO >0002 to unmask INT2 such that the VDP interrupts are passed to the processor.

So is MESS possibly not setting the power-up state of the 9901 correctly?

Stuart.

---

From: Jeffrey White <[email-masked]>
Date: Wed, 6 Jul 2011 01:19:40 -0700 (PDT)

Pre-emptive strike?

I think the clues to a solution are in the cassette routines, which do disable 
the VDP interrupt with SBZ >0002 at 13D4 while setting up the internal timer of 
the 9901 for the cassette interrupt.

There is also the possibility that a program could get play with the VDP and 
9901 settings in such a way to service a VDP interrupt while /INT2 is masked.  I 
will have to think about that one. 

Jeff White

Sent: Tue, July 5, 2011 5:08:04 PM

Here's another technical challenge, maybe some of you can give me a hint or 
convince me of another conclusion.

Question: What is the meaning of the SBO >0002 line in the TI console ROM at 
location 094A?

Address >0004 (bit 2) of the CRU is named /INT2 and is connected to /INT of the 
VDP.

I had a look at Heiner Martin's "TI Intern" book (many of you certainly know 
about it), and I found the comment "Clear VDP interrupt". This sounds plausible, 
but it can't be true.

The problem is that the TMS9901 has a dual function on its interrupt line bits. 
You can read their state with TB, and you can load a value into them with SBO 
and SBZ. However, loading a value does not change the input latch contents - it 
sets or resets the mask for this input. The mask is ANDed to the inverted latch 
value, so you can attach or detach interrupt inputs with SBO/SBZ. (Also see 
Figure 3 in the description TMS9901.pdf on WhTech.)

I put a printf into the MESS emulation and found that (as expected) the mask for 
/INT2 is never set to 0 but is always 1. In contrast, if the value had been 0 
(so SBO would make sense), the /INT2 would have been masked away, which would 
block VDP interrupts, so this code would never be reached. 

It may sound a bit bold, but I conclude that the line in the console ROM does 
not make sense. Maybe the engineers misunderstood the 9901 operation at that 
point.

Any other ideas?

Michael

---

From: [email-masked]
Date: Wed, 6 Jul 2011 10:19:05 +0000 (UTC)

Could it be also for GROM/VDP interaction like the GPL MOVE command or the GPL I/O command that is the core of the Cassette code? 

Also code that was never supported was the GPL commands XML into DSR space or test cards the TI used and never released? 

----- Original Message -----
From: "Jeffrey White" <[email-masked]> 
To: [email-masked] 
Sent: Wednesday, July 6, 2011 1:19:40 AM 
Subject: Re: [TI994A] CRU / TMS9901 challenging question 

Pre-emptive strike? 

I think the clues to a solution are in the cassette routines, which do disable the VDP interrupt with SBZ >0002 at 13D4 while setting up the internal timer of the 9901 for the cassette interrupt. 

There is also the possibility that a program could get play with the VDP and 9901 settings in such a way to service a VDP interrupt while /INT2 is masked. I will have to think about that one. 

Jeff White 

Any other ideas? 

Michael